IRIS
CURATELLI, FRANCESCO
 Distribuzione geografica
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Continente #
EU - Europa 10.605
Totale 10.605
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Nazione #
IT - Italia 10.605
Totale 10.605
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Città #
Genova 8.214
Rapallo 1.194
Genoa 851
Vado Ligure 319
Bordighera 27
Totale 10.605
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Nome #
A Holographic Memory Approach for Pollution Forecasting in a High-Density Urban Environment 155
The Journey: A Service-Based Adaptive Serious Game on Probability 150
A Reconfigurable Wiring Algorithm for Three-Layer Maze Routing 149
Characterization of the Thermal Behaviour in ICs 144
S-CFG: a Representation Model for System Synthesis 141
Three-dimensional Transient Thermal Simulation: Application to Delayed Short Circuit Protection in Power IC's 140
A Symbolic Switchbox Router for Macrocell IC's Design 140
Symbolic Generation of Constrained Random Logic Cells 139
Implementation of an efficient algorithm for VLSI design rule checking on a 2-D mesh of transputers 139
Mapping Linear Algebra Algorithms into Array Processors: a Case Study 137
Improving Cognitive Abilities and e-Inclusion in Children with Cerebral Palsy 136
Efficient Technique for Partitioning and Programming Linear Algebra Algorithms on Concurrent VLSI Architectures 135
Paths for Cognitive Rehabilitation: From Reality to Educational Software, to Serious Games, to Reality Again 130
An Algorithm for the Definition of Routing Regions in VLSI Design 129
Specification and Management of Timing Constraints in Behavioral VHDL 128
A Method for Computing the Number of Iterations in Data Dependent Loops 126
A Message-Passing Communication Scheme for System Specification 122
A Method for Programming Matrix Algorithms in Array Processors 122
Region Definition and Ordering for Macrocells with Unconstrained Placement 121
Transient Thermal Simulation and its Use in Power IC Design 121
Enhancing Digital Inclusion with an English Pseudo-Syllabic Keyboard 119
Competitive Learning Methods for Efficient Vector Quantizations 1363 in a Speech Recognition Environment 118
Implementation Issues for Congestion Control in ATM Networks 118
Designing a Serious Game as a Diagnostic Tool 118
A Data-Flow Graph Representation for HDL Specification 117
Symbolic Compaction of Digital CMOS Cells 117
Involving Cognitively Disabled Young People in Focused Mini SGs Design: A Case Study 116
A Tile-Expansion Router 114
Time-Domain Segmentation and Labelling of Speech with Fuzzy-Logic Post-Correction Rules 112
A Powerful Pseudo-Syllabic Text Entry Paradigm 112
Stationary and Transient Thermal Simulation and its Use in Power IC Design 111
Implementation and Evaluation of Genetic Algorithms for System Partitioning 110
Implementation of Efficient Strategies for Cell Generation in VLSI Design 109
A Parallel Approach to Symbolic Layout Compaction of Digital CMOS Cells 106
Handwritten Digit Recognition by means of an Holographic Associative Memory 105
A Symbolic Cell Synthesizer for CMOS IC Design 105
Neural Algorithms for Cell Placement in VLSI Design 105
A smart mobility serious game concept and business development study 105
Switchbox Routing with Rerouting Capabilities in VLSI Design 103
High Efficiency Solution of Triangular System Equations on a 2-D Array of Transputers 103
Optimization Strategies for the Symbolic Compaction of Digital CMOS Cells 103
Parallel Symbolic Compaction of Digital CMOS Cells on a 2-D Mesh of Transputers 102
A Graph-Based Tool for Compacted Channel Routing 101
Pre-Placement of VLSI Blocks through Learning Neural Networks 101
SPEAR A Modular Tool for Speech Signal Processing and Recognition 101
Hierarchical Management of VLSI Cells at Different Description Levels 101
Functional Simulation of VLSI Architectures 100
An Object-Oriented Framework for the Design of VLSI Cells 98
Speech Parameter Extraction by a Cooperative Feature and Pattern Selector Approach 98
A behavioural simulator and its use for the validation of hypercube architectures 98
A Distributed DRC program for IC Layout Verification 97
Improving Text Entry Performance for Spanish-Speaking Non-Expert and Impaired Users 97
A Cooperative Computational Geometry/Statistical Method for Pattern & Feature Reduction 96
Heuristic Strategies for Switchbox Routing in VLSI Design 96
Design Criteria for Educational Tools to Overcome Mathematics Learning Difficulties 96
Forecasting of Atmospheric Pollution Levels with Neural Networks 94
Efficient Management of Complex Elements in Physical IC Design 94
Automatic Generation of Symbolic Cells from a Net-List Description 93
Safe Sequencing of Concurrent Events in Behavioural Simulation 93
CAD Support for System-level Synthesis 93
Real-time Multi-tasking in Software Synthesis for DSP Based Systems 92
Tastiere IT-Skip (Italiano), EN-Skip (Inglese), Es-Skip (Spagnolo), Tablet-Skip (Tablet per C.A.A.) su piattaforma SKIP 1.2. 91
A Java Simulation Environment for System Level Synthesis 89
Keystroke Saving in a Language with Highly Transparent Orthography 89
An Holographic Neural Network-Based Method for Recognition of Handwritten Numerals 87
Synthesis of VLSI Systems from VHDL Behavioral Descriptions 86
String Correction For Text Streams Using Associative Memories 85
A Parallel Associative Memory Architecture for Phone Estimation 83
Mapping Large Wavefront Algorithms onto Processor Square Meshes of Fixed Size 83
System-Level Modeling of an ATM Node in VHDL 83
SKIP 0.1 83
Data Communication Management in System Specification 83
General Overview of the SPEAR Speech Recognition System 82
A CGI Tool for Multiple Access to VHDL CAD Tools 81
Development of CAD Applications Using Different Languages: a Comparative Analysis 81
SKIP 0.3 81
Percorsi e Software Didattici per il Recupero di Difficoltà Cognitive in Ambito Logico-Matematico 80
Software Synthesis for Information processing Systems 79
Transputer Application for Integrated Circuit Layout Verification 79
Simulation of Neural Networks for the Resolution of Optimization Problems 79
SALT 1.0 78
SAGE 1.0 78
Wiring Strategies in VLSI Design 77
A Hierarchical Control-Flow Model for System Synthesis 77
Esperienze di Comunità di Apprendimento Virtuali 77
ERG 1.1 75
CoLT 1.0 74
An Hybrid Parallel Associative Memory/DTW Based System for Speech Recognition 71
A Powerful Data-Flow Graph Representation for Basic Blocks 71
Laboratori Reali e Virtuali: l'E-learning per una Didattica Cooperativa 69
Evaluation of Communication Performances in Hypercube Architectures 69
Optimization Strategies in Symbolic Compaction 68
Global Scheduling Techniques for Behavioral Synthesis 68
Synthesis Strategies from VHDL Descriptions of DSP Circuits 67
Laboratori e Tutorati: Proposte per Affrontare le Difficoltà in Matematica dalla Scuola Primaria all'Università 67
ArTIC 1.0 66
Schiere di Transputer Programmati a Fronte d'Onda in Linguaggio OCCAM 65
Mapping Large Wavefront Algorithms to Processor Square Meshes of Fixed Size 64
Methods and Tools for the Design of Microelectronic Systems 63
Mondi Reali e Virtuali per lo Sviluppo Cognitivo di Ragazzi Disabili 63
Totale 9.962
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Categoria #
all - tutte 25.633
article - articoli 7.551
book - libri 0
conference - conferenze 13.043
curatela - curatele 0
other - altro 1.709
patent - brevetti 0
selected - selezionate 0
volume - volumi 3.330
Totale 51.266
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20202.670 0 0 0 139 247 249 523 140 214 531 503 124
2020/2021687 79 38 29 43 23 87 33 45 119 55 66 70
2021/20221.336 23 90 55 206 43 126 44 378 47 133 27 164
2022/20231.395 136 106 33 180 219 263 4 92 238 9 101 14
2023/2024555 21 104 9 64 38 72 32 44 27 7 30 107
2024/2025440 148 157 88 47 0 0 0 0 0 0 0 0
Totale 10.642