IRIS
CURATELLI, FRANCESCO
 Distribuzione geografica
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Continente #
EU - Europa 10.053
Totale 10.053
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Nazione #
IT - Italia 10.053
Totale 10.053
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Città #
Genova 8.214
Rapallo 1.194
Genoa 618
Bordighera 27
Totale 10.053
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Nome #
A Holographic Memory Approach for Pollution Forecasting in a High-Density Urban Environment 143
A Reconfigurable Wiring Algorithm for Three-Layer Maze Routing 142
The Journey: A Service-Based Adaptive Serious Game on Probability 141
Characterization of the Thermal Behaviour in ICs 139
S-CFG: a Representation Model for System Synthesis 139
Three-dimensional Transient Thermal Simulation: Application to Delayed Short Circuit Protection in Power IC's 138
Implementation of an efficient algorithm for VLSI design rule checking on a 2-D mesh of transputers 138
Mapping Linear Algebra Algorithms into Array Processors: a Case Study 135
A Symbolic Switchbox Router for Macrocell IC's Design 133
Improving Cognitive Abilities and e-Inclusion in Children with Cerebral Palsy 130
Symbolic Generation of Constrained Random Logic Cells 128
Efficient Technique for Partitioning and Programming Linear Algebra Algorithms on Concurrent VLSI Architectures 128
An Algorithm for the Definition of Routing Regions in VLSI Design 125
Specification and Management of Timing Constraints in Behavioral VHDL 124
Region Definition and Ordering for Macrocells with Unconstrained Placement 120
Transient Thermal Simulation and its Use in Power IC Design 119
A Method for Computing the Number of Iterations in Data Dependent Loops 119
Paths for Cognitive Rehabilitation: From Reality to Educational Software, to Serious Games, to Reality Again 117
A Message-Passing Communication Scheme for System Specification 116
Symbolic Compaction of Digital CMOS Cells 116
Implementation Issues for Congestion Control in ATM Networks 115
Competitive Learning Methods for Efficient Vector Quantizations 1363 in a Speech Recognition Environment 114
A Method for Programming Matrix Algorithms in Array Processors 113
Designing a Serious Game as a Diagnostic Tool 113
A Tile-Expansion Router 110
Involving Cognitively Disabled Young People in Focused Mini SGs Design: A Case Study 110
A Data-Flow Graph Representation for HDL Specification 109
Enhancing Digital Inclusion with an English Pseudo-Syllabic Keyboard 109
Time-Domain Segmentation and Labelling of Speech with Fuzzy-Logic Post-Correction Rules 108
Stationary and Transient Thermal Simulation and its Use in Power IC Design 108
Implementation and Evaluation of Genetic Algorithms for System Partitioning 105
Implementation of Efficient Strategies for Cell Generation in VLSI Design 105
Handwritten Digit Recognition by means of an Holographic Associative Memory 101
Switchbox Routing with Rerouting Capabilities in VLSI Design 101
Neural Algorithms for Cell Placement in VLSI Design 101
Optimization Strategies for the Symbolic Compaction of Digital CMOS Cells 101
A Powerful Pseudo-Syllabic Text Entry Paradigm 101
Parallel Symbolic Compaction of Digital CMOS Cells on a 2-D Mesh of Transputers 100
A Symbolic Cell Synthesizer for CMOS IC Design 100
A Parallel Approach to Symbolic Layout Compaction of Digital CMOS Cells 99
SPEAR A Modular Tool for Speech Signal Processing and Recognition 99
Hierarchical Management of VLSI Cells at Different Description Levels 99
Functional Simulation of VLSI Architectures 98
A smart mobility serious game concept and business development study 98
High Efficiency Solution of Triangular System Equations on a 2-D Array of Transputers 98
A Graph-Based Tool for Compacted Channel Routing 97
Pre-Placement of VLSI Blocks through Learning Neural Networks 96
An Object-Oriented Framework for the Design of VLSI Cells 95
Speech Parameter Extraction by a Cooperative Feature and Pattern Selector Approach 95
Heuristic Strategies for Switchbox Routing in VLSI Design 94
Forecasting of Atmospheric Pollution Levels with Neural Networks 93
Efficient Management of Complex Elements in Physical IC Design 93
Improving Text Entry Performance for Spanish-Speaking Non-Expert and Impaired Users 92
A Cooperative Computational Geometry/Statistical Method for Pattern & Feature Reduction 91
A Distributed DRC program for IC Layout Verification 91
Real-time Multi-tasking in Software Synthesis for DSP Based Systems 90
Safe Sequencing of Concurrent Events in Behavioural Simulation 90
Automatic Generation of Symbolic Cells from a Net-List Description 89
Design Criteria for Educational Tools to Overcome Mathematics Learning Difficulties 89
A behavioural simulator and its use for the validation of hypercube architectures 88
CAD Support for System-level Synthesis 87
Keystroke Saving in a Language with Highly Transparent Orthography 86
An Holographic Neural Network-Based Method for Recognition of Handwritten Numerals 84
Synthesis of VLSI Systems from VHDL Behavioral Descriptions 84
String Correction For Text Streams Using Associative Memories 82
A Java Simulation Environment for System Level Synthesis 81
Mapping Large Wavefront Algorithms onto Processor Square Meshes of Fixed Size 79
System-Level Modeling of an ATM Node in VHDL 79
Development of CAD Applications Using Different Languages: a Comparative Analysis 78
SKIP 0.1 78
Data Communication Management in System Specification 78
General Overview of the SPEAR Speech Recognition System 78
Software Synthesis for Information processing Systems 77
A Parallel Associative Memory Architecture for Phone Estimation 76
Tastiere IT-Skip (Italiano), EN-Skip (Inglese), Es-Skip (Spagnolo), Tablet-Skip (Tablet per C.A.A.) su piattaforma SKIP 1.2. 76
Simulation of Neural Networks for the Resolution of Optimization Problems 76
Transputer Application for Integrated Circuit Layout Verification 75
SKIP 0.3 75
A CGI Tool for Multiple Access to VHDL CAD Tools 74
Wiring Strategies in VLSI Design 74
Percorsi e Software Didattici per il Recupero di Difficoltà Cognitive in Ambito Logico-Matematico 72
SALT 1.0 71
SAGE 1.0 71
ERG 1.1 70
A Hierarchical Control-Flow Model for System Synthesis 70
CoLT 1.0 68
Optimization Strategies in Symbolic Compaction 66
An Hybrid Parallel Associative Memory/DTW Based System for Speech Recognition 66
Evaluation of Communication Performances in Hypercube Architectures 66
Synthesis Strategies from VHDL Descriptions of DSP Circuits 65
Global Scheduling Techniques for Behavioral Synthesis 64
A Powerful Data-Flow Graph Representation for Basic Blocks 63
Esperienze di Comunità di Apprendimento Virtuali 62
Schiere di Transputer Programmati a Fronte d'Onda in Linguaggio OCCAM 61
Mapping Large Wavefront Algorithms to Processor Square Meshes of Fixed Size 61
ArTIC 1.0 61
Laboratori Reali e Virtuali: l'E-learning per una Didattica Cooperativa 61
Methods and Tools for the Design of Microelectronic Systems 60
Layout Synthesis Strategies in Silicon Compilation 57
Mondi Reali e Virtuali per lo Sviluppo Cognitivo di Ragazzi Disabili 57
Totale 9.457
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Categoria #
all - tutte 21.875
article - articoli 6.485
book - libri 0
conference - conferenze 11.159
curatela - curatele 0
other - altro 1.416
patent - brevetti 0
selected - selezionate 0
volume - volumi 2.815
Totale 43.750
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/2019355 0 0 0 0 0 0 0 0 0 0 211 144
2019/20202.947 83 77 117 139 247 249 523 140 214 531 503 124
2020/2021687 79 38 29 43 23 87 33 45 119 55 66 70
2021/20221.336 23 90 55 206 43 126 44 378 47 133 27 164
2022/20231.395 136 106 33 180 219 263 4 92 238 9 101 14
2023/2024443 21 104 9 64 38 72 32 44 27 7 25 0
Totale 10.090