In this paper, a powerful communication scheme is introduced to efficiently meet different communication requirements for behavioural synthesis from VHDL. The algorithmic description of the system behaviour is specified through a set of cooperating VHDL processes. Communication between processes is provided by the definition of a message--passing communication scheme, to efficiently manage both synchronised and unsynchronised data exchange. A way to effectively map message passing to shared memory for system synthesis is also presented. The proposed data communication scheme has been successfully tested with the VHDL model of the congestion control of an ATM node.
Data Communication Management in System Specification
CURATELLI, FRANCESCO;CHIRICO M.
1999-01-01
Abstract
In this paper, a powerful communication scheme is introduced to efficiently meet different communication requirements for behavioural synthesis from VHDL. The algorithmic description of the system behaviour is specified through a set of cooperating VHDL processes. Communication between processes is provided by the definition of a message--passing communication scheme, to efficiently manage both synchronised and unsynchronised data exchange. A way to effectively map message passing to shared memory for system synthesis is also presented. The proposed data communication scheme has been successfully tested with the VHDL model of the congestion control of an ATM node.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
