CURATELLI, FRANCESCO
CURATELLI, FRANCESCO
100026 - Dipartimento di Ingegneria navale, elettrica, elettronica e delle telecomunicazioni
A behavioural simulator and its use for the validation of hypercube architectures
1988-01-01 Curatelli, Francesco; Bisio, G. M.; Borghero, G.; DI ZITTI, Ermanno
A CGI Tool for Multiple Access to VHDL CAD Tools
1998-01-01 Curatelli, Francesco; Mangeruca, L; Motta, L; Ghezzi, F; Guido, D.
A Cooperative Computational Geometry/Statistical Method for Pattern & Feature Reduction
1999-01-01 O., MAYORA IBARRA; Curatelli, Francesco
A Data-Flow Graph Representation for HDL Specification
1998-01-01 Curatelli, Francesco; Mangeruca, L.; Chirico, M.
A Distributed DRC program for IC Layout Verification
1990-01-01 Paganini, M; Chirico, M; Caviglia, Daniele; Curatelli, Francesco; Barzaghi, M; Bisio, G. M.
A Graph-Based Tool for Compacted Channel Routing
1992-01-01 Curatelli, Francesco; Caviglia, Daniele; Cornero, M; Bisio, G. M.
A Hierarchical Control-Flow Model for System Synthesis
1998-01-01 Curatelli, Francesco; Mangeruca, L.; Chirico, M.
A Holographic Memory Approach for Pollution Forecasting in a High-Density Urban Environment
2001-01-01 Curatelli, Francesco; MAYORA IBARRA, Oscar
A Java Simulation Environment for System Level Synthesis
1999-01-01 Curatelli, Francesco; Mangeruca, L; Motta, L.
A Message-Passing Communication Scheme for System Specification
1999-01-01 Curatelli, Francesco; Mangeruca, L; Chirico, M.
A Method for Computing the Number of Iterations in Data Dependent Loops
2006-01-01 Curatelli, Francesco; Mangeruca, Leonardo
A Method for Programming Matrix Algorithms in Array Processors
1988-01-01 Bisio, G. M.; Arduini, F; Curatelli, Francesco; DI ZITTI, E; Parodi, G. C.; Zini, A.
A Parallel Approach to Symbolic Layout Compaction of Digital CMOS Cells
1992-01-01 Barzaghi, M.; Caviglia, Daniele; Chirico, M.; Curatelli, Francesco; Bisio, G. M.; Prossen, S.; Stefani, L.
A Parallel Associative Memory Architecture for Phone Estimation
1999-01-01 MAYORA IBARRA, O.; Curatelli, Francesco
A Powerful Data-Flow Graph Representation for Basic Blocks
1998-01-01 Curatelli, Francesco; Mangeruca, L; Chirico, M.
A Powerful Pseudo-Syllabic Text Entry Paradigm
2006-01-01 Curatelli, Francesco; Martinengo, Chiara
A Reconfigurable Wiring Algorithm for Three-Layer Maze Routing
1989-01-01 Curatelli, Francesco; Antognetti, P.
A smart mobility serious game concept and business development study
2016-01-01 Bellotti, Francesco; Berta, Riccardo; DE GLORIA, Alessandro; Dange, GAUTAM RAVINDRA; Paranthaman, P. K.; Curatelli, Francesco; Martinengo, Chiara; Barabino, Giulio; Sciutto, Giuseppe; Demirtzis, E.; Hausler, F.
A Symbolic Cell Synthesizer for CMOS IC Design
1988-01-01 Costa, R; Curatelli, Francesco; Caviglia, Daniele; Bisio, G. M.
A Symbolic Switchbox Router for Macrocell IC's Design
1989-01-01 Curatelli, Francesco; Bisio, G. M.
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| A behavioural simulator and its use for the validation of hypercube architectures | 1-gen-1988 | Curatelli, Francesco; Bisio, G. M.; Borghero, G.; DI ZITTI, Ermanno | |
| A CGI Tool for Multiple Access to VHDL CAD Tools | 1-gen-1998 | Curatelli, Francesco; Mangeruca, L; Motta, L; Ghezzi, F; Guido, D. | |
| A Cooperative Computational Geometry/Statistical Method for Pattern & Feature Reduction | 1-gen-1999 | O., MAYORA IBARRA; Curatelli, Francesco | |
| A Data-Flow Graph Representation for HDL Specification | 1-gen-1998 | Curatelli, Francesco; Mangeruca, L.; Chirico, M. | |
| A Distributed DRC program for IC Layout Verification | 1-gen-1990 | Paganini, M; Chirico, M; Caviglia, Daniele; Curatelli, Francesco; Barzaghi, M; Bisio, G. M. | |
| A Graph-Based Tool for Compacted Channel Routing | 1-gen-1992 | Curatelli, Francesco; Caviglia, Daniele; Cornero, M; Bisio, G. M. | |
| A Hierarchical Control-Flow Model for System Synthesis | 1-gen-1998 | Curatelli, Francesco; Mangeruca, L.; Chirico, M. | |
| A Holographic Memory Approach for Pollution Forecasting in a High-Density Urban Environment | 1-gen-2001 | Curatelli, Francesco; MAYORA IBARRA, Oscar | |
| A Java Simulation Environment for System Level Synthesis | 1-gen-1999 | Curatelli, Francesco; Mangeruca, L; Motta, L. | |
| A Message-Passing Communication Scheme for System Specification | 1-gen-1999 | Curatelli, Francesco; Mangeruca, L; Chirico, M. | |
| A Method for Computing the Number of Iterations in Data Dependent Loops | 1-gen-2006 | Curatelli, Francesco; Mangeruca, Leonardo | |
| A Method for Programming Matrix Algorithms in Array Processors | 1-gen-1988 | Bisio, G. M.; Arduini, F; Curatelli, Francesco; DI ZITTI, E; Parodi, G. C.; Zini, A. | |
| A Parallel Approach to Symbolic Layout Compaction of Digital CMOS Cells | 1-gen-1992 | Barzaghi, M.; Caviglia, Daniele; Chirico, M.; Curatelli, Francesco; Bisio, G. M.; Prossen, S.; Stefani, L. | |
| A Parallel Associative Memory Architecture for Phone Estimation | 1-gen-1999 | MAYORA IBARRA, O.; Curatelli, Francesco | |
| A Powerful Data-Flow Graph Representation for Basic Blocks | 1-gen-1998 | Curatelli, Francesco; Mangeruca, L; Chirico, M. | |
| A Powerful Pseudo-Syllabic Text Entry Paradigm | 1-gen-2006 | Curatelli, Francesco; Martinengo, Chiara | |
| A Reconfigurable Wiring Algorithm for Three-Layer Maze Routing | 1-gen-1989 | Curatelli, Francesco; Antognetti, P. | |
| A smart mobility serious game concept and business development study | 1-gen-2016 | Bellotti, Francesco; Berta, Riccardo; DE GLORIA, Alessandro; Dange, GAUTAM RAVINDRA; Paranthaman, P. K.; Curatelli, Francesco; Martinengo, Chiara; Barabino, Giulio; Sciutto, Giuseppe; Demirtzis, E.; Hausler, F. | |
| A Symbolic Cell Synthesizer for CMOS IC Design | 1-gen-1988 | Costa, R; Curatelli, Francesco; Caviglia, Daniele; Bisio, G. M. | |
| A Symbolic Switchbox Router for Macrocell IC's Design | 1-gen-1989 | Curatelli, Francesco; Bisio, G. M. |