Implementation of an efficient algorithm for VLSI design rule checking on a 2-D mesh of transputers

A design rule checking program for VLSI circuit layouts with Manhattan geometries is presented. The layout model is described along with the way the authors implemented the check through few and simple primitives for describing parameteric rules. A single main function for the geometrical test is outlined and how the authors succeeded in limiting the checking time through an algorithm characterized by a linear computational complexity is given. How it was mapped on a mesh of transputers is also discussed.