The efficiency of a symbolic compactor is closely related to the quality of the physical layout produced. In particular, a reduction of the dimensions of the chip can be achieved by eliminating useless components, optimizing wires, and performing a proper rearrangement of the components positions. In this paper, some optimization strategies are described which make it possible to achieve significant lrnprovements in the physical layout produced by a symbolic compactor.
Optimization Strategies in Symbolic Compaction
CURATELLI, FRANCESCO;CAVIGLIA, DANIELE;CHIRICO M.;
1993-01-01
Abstract
The efficiency of a symbolic compactor is closely related to the quality of the physical layout produced. In particular, a reduction of the dimensions of the chip can be achieved by eliminating useless components, optimizing wires, and performing a proper rearrangement of the components positions. In this paper, some optimization strategies are described which make it possible to achieve significant lrnprovements in the physical layout produced by a symbolic compactor.
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