Sfoglia per Autore
A VLSI architecture for a Prolog machine
1988-01-01 Valle, Maurizio; DE GLORIA, Alessandro; Chirico, M.; Antognetti, P.
CMOS Circuit Design of a Programmable Neural Net Classifier of Exclusive Classes
1989-01-01 Caviglia, Daniele; Bisio, Giacomo; P., Daglio; Valle, Maurizio
Wiring Strategies in VLSI Design
1989-01-01 Curatelli, Francesco; Valle, Maurizio
Simulation of Neural Networks for the Resolution of Optimization Problems
1989-01-01 Bisio, G. M.; Caviglia, Daniele; Chirico, M; Curatelli, Francesco; Valle, Maurizio
An evaluation system for Prolog dedicated processors
1990-01-01 DE GLORIA, Alessandro; Valle, Maurizio; Chirico, M.; Moneta, C.
Effects of weight discretization on the back propagation learning method: Algorithm design and hardware realization
1990-01-01 Caviglia, Daniele; Valle, Maurizio; Bisio, Giacomo
An experimental analog VLSI neural chip with on-chip back-propagation learning
1992-01-01 Valle, M.; Caviglia, D. D.; Bisio, G. M.
Design of a CMOS ASIC chip featuring analog neural computational primitives
1992-01-01 Valle, Maurizio; Caviglia, Daniele; Bisio, Giacomo
An analog VLSI neural network character recognition system: the feature extraction module
1994-01-01 Caviglia, Daniele; Rossi, A; Vincentelli, M; Valle, Maurizio
Feature extraction circuit for optical character recognition
1994-01-01 Caviglia, Daniele; Valle, Maurizio; A., Rossi; M., Vincentelli; G., Bo; P., Colangelo; P., Pedrazzi; A. M., Colla
Non-linear circuit effects on analog VLSI neural network implementations
1994-01-01 Onorato, M; Valle, Maurizio; Caviglia, Daniele; Bisio, Giacomo
VHDL-based design methodology: The design experience of an high performance ASIC chip
1994-01-01 Valle, Maurizio; Cornero, Marco; Nateri, Giovanni; Caviglia, Daniele; Briozzo, Luigi
An analog VLSI neural network for real-time image processing in industrial applications
1994-01-01 Valle, Maurizio; Onorato, M; Oddone, F; Caviglia, Daniele; Bisio, Giacomo
An ASIC design for real-time image processing in industrial applications
1995-01-01 Valle, M.; Nateri, G.; Caviglia, D. D.; Bisio, G. M.; Briozzo, L.
A Current Mode CMOS Multi Layer Perceptron Chip
1996-01-01 G. M., Bo; Caviglia, Daniele; Valle, Maurizio
Application of hierarchical neural networks to pattern recognition for quality control analysis in steel-industry plants
1996-01-01 Valle, Maurizio; Baratta, Daniela; Caviglia, Daniele
An Experimental Analog VLSI Neural Network with On-Chip Back-Propagation Learning
1996-01-01 Valle, Maurizio; Caviglia, Daniele; Bisio, Giacomo
A VLSI Image Processing Architecture Dedicated to Real-Time Quality Control Analysis in an Industrial Plant
1996-01-01 Valle, Maurizio; L., Raffo; Caviglia, Daniele; Bisio, Giacomo
Programmed neural module
1996-01-01 R., Parenti; D., Baratta; Caviglia, Daniele; Valle, Maurizio
A hardware implementation of hierarchical neural networks for real-time quality control systems in industrial applications
1997-01-01 Baratta, D.; Bo, G. M.; Caviglia, Daniele; Valle, Maurizio; Canepa, G.; Parenti, R.; Pernio, C.
Titolo | Data di pubblicazione | Autore(i) | File |
---|---|---|---|
A VLSI architecture for a Prolog machine | 1-gen-1988 | Valle, Maurizio; DE GLORIA, Alessandro; Chirico, M.; Antognetti, P. | |
CMOS Circuit Design of a Programmable Neural Net Classifier of Exclusive Classes | 1-gen-1989 | Caviglia, Daniele; Bisio, Giacomo; P., Daglio; Valle, Maurizio | |
Wiring Strategies in VLSI Design | 1-gen-1989 | Curatelli, Francesco; Valle, Maurizio | |
Simulation of Neural Networks for the Resolution of Optimization Problems | 1-gen-1989 | Bisio, G. M.; Caviglia, Daniele; Chirico, M; Curatelli, Francesco; Valle, Maurizio | |
An evaluation system for Prolog dedicated processors | 1-gen-1990 | DE GLORIA, Alessandro; Valle, Maurizio; Chirico, M.; Moneta, C. | |
Effects of weight discretization on the back propagation learning method: Algorithm design and hardware realization | 1-gen-1990 | Caviglia, Daniele; Valle, Maurizio; Bisio, Giacomo | |
An experimental analog VLSI neural chip with on-chip back-propagation learning | 1-gen-1992 | Valle, M.; Caviglia, D. D.; Bisio, G. M. | |
Design of a CMOS ASIC chip featuring analog neural computational primitives | 1-gen-1992 | Valle, Maurizio; Caviglia, Daniele; Bisio, Giacomo | |
An analog VLSI neural network character recognition system: the feature extraction module | 1-gen-1994 | Caviglia, Daniele; Rossi, A; Vincentelli, M; Valle, Maurizio | |
Feature extraction circuit for optical character recognition | 1-gen-1994 | Caviglia, Daniele; Valle, Maurizio; A., Rossi; M., Vincentelli; G., Bo; P., Colangelo; P., Pedrazzi; A. M., Colla | |
Non-linear circuit effects on analog VLSI neural network implementations | 1-gen-1994 | Onorato, M; Valle, Maurizio; Caviglia, Daniele; Bisio, Giacomo | |
VHDL-based design methodology: The design experience of an high performance ASIC chip | 1-gen-1994 | Valle, Maurizio; Cornero, Marco; Nateri, Giovanni; Caviglia, Daniele; Briozzo, Luigi | |
An analog VLSI neural network for real-time image processing in industrial applications | 1-gen-1994 | Valle, Maurizio; Onorato, M; Oddone, F; Caviglia, Daniele; Bisio, Giacomo | |
An ASIC design for real-time image processing in industrial applications | 1-gen-1995 | Valle, M.; Nateri, G.; Caviglia, D. D.; Bisio, G. M.; Briozzo, L. | |
A Current Mode CMOS Multi Layer Perceptron Chip | 1-gen-1996 | G. M., Bo; Caviglia, Daniele; Valle, Maurizio | |
Application of hierarchical neural networks to pattern recognition for quality control analysis in steel-industry plants | 1-gen-1996 | Valle, Maurizio; Baratta, Daniela; Caviglia, Daniele | |
An Experimental Analog VLSI Neural Network with On-Chip Back-Propagation Learning | 1-gen-1996 | Valle, Maurizio; Caviglia, Daniele; Bisio, Giacomo | |
A VLSI Image Processing Architecture Dedicated to Real-Time Quality Control Analysis in an Industrial Plant | 1-gen-1996 | Valle, Maurizio; L., Raffo; Caviglia, Daniele; Bisio, Giacomo | |
Programmed neural module | 1-gen-1996 | R., Parenti; D., Baratta; Caviglia, Daniele; Valle, Maurizio | |
A hardware implementation of hierarchical neural networks for real-time quality control systems in industrial applications | 1-gen-1997 | Baratta, D.; Bo, G. M.; Caviglia, Daniele; Valle, Maurizio; Canepa, G.; Parenti, R.; Pernio, C. |
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