Analog VLSI implementations of artificial neural networks are usually considered efficient for the small area and the low power consumption they require, but very poor in terms of programmability. In this paper, we present an approach to the design of analog VLSI neural information-processing systems with on-chip learning capabilities. We describe a set of analog circuits for implementing the neural computational primitives of a Multi-Layer Perceptron, including the ones supporting a gradient-based learning algorithm (Back Propagation). Only supervision tasks are managed off chip. An experimental chip has been designed and fabricated using a standard digital 1.5 um CMOS N-well technology. The chip contains 4 neurons and 32 synapses organized into a single-layer architecture with 8 inputs and 4 outputs. Measures illustrating the chip behavior during learning are reported.
An Experimental Analog VLSI Neural Network with On-Chip Back-Propagation Learning
VALLE, MAURIZIO;CAVIGLIA, DANIELE;BISIO, GIACOMO
1996-01-01
Abstract
Analog VLSI implementations of artificial neural networks are usually considered efficient for the small area and the low power consumption they require, but very poor in terms of programmability. In this paper, we present an approach to the design of analog VLSI neural information-processing systems with on-chip learning capabilities. We describe a set of analog circuits for implementing the neural computational primitives of a Multi-Layer Perceptron, including the ones supporting a gradient-based learning algorithm (Back Propagation). Only supervision tasks are managed off chip. An experimental chip has been designed and fabricated using a standard digital 1.5 um CMOS N-well technology. The chip contains 4 neurons and 32 synapses organized into a single-layer architecture with 8 inputs and 4 outputs. Measures illustrating the chip behavior during learning are reported.
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