Design of a CMOS ASIC chip featuring analog neural computational primitives

An ASIC analog chip which implements the basic computational primitives of a neural model with on-chip learning has been designed and fabricated using a 1.5 μm CMOS technology. The chip contains about 3K transistors arranged into a matrix of 8×4 synapses fully connected to 4 neurons. Using the chip as basic module, it is possible to obtain more complex networks. The adaptive architecture hosted by the analog continuous-time CMOS VLSI circuits has been devised to support high-level neural computational models (e.g. Back Propagation). Formal variables of the algorithm are translated into electrical ones. Neural circuits feature a full analog and adaptive behaviour, and directly map into hardware the basic neural computational primitives. Analog adaptive neural computation does not require high computational accuracy. Its implementation through full custom circuits is attractive, as it is efficient and compact.