An analog VLSI neural network integrated circuit is presented. It consist of a feedforward multi layer perceptron (MLP) network with 64 inputs, 64 hidden neurons and 10 outputs. The computational cells have been designed by using the current mode approach and weak inversion biased MOS transistors to reduce the occupied area and power consumption. The processing delay is less than 2 μs and the total average power consumption is around 200 mW. This is equivalent to a computational power of about 2.5×109 connections per second. The chip can be employed in a chip-in-the-loop neural architecture

A Current Mode CMOS Multi Layer Perceptron Chip

CAVIGLIA, DANIELE;VALLE, MAURIZIO
1996

Abstract

An analog VLSI neural network integrated circuit is presented. It consist of a feedforward multi layer perceptron (MLP) network with 64 inputs, 64 hidden neurons and 10 outputs. The computational cells have been designed by using the current mode approach and weak inversion biased MOS transistors to reduce the occupied area and power consumption. The processing delay is less than 2 μs and the total average power consumption is around 200 mW. This is equivalent to a computational power of about 2.5×109 connections per second. The chip can be employed in a chip-in-the-loop neural architecture
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11567/201538
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