In this paper a reconfigurable analog VLSI neural network architecture is presented. The analog architecture implements a Multi-Layer Perceptron whose topology can be programmed without any modification of the off-chip connections. The architecture is scaleable and modular since it is based on a single-chip configurable basic module. To obtain a robust behaviour with respect to noise and errors introduced in the computation by analog circuits, we use non-linear synapses and linear neurons as neural primitives.

A reconfigurable analog VLSI neural network architecture with non linear synapses

CAVIGLIA, DANIELE;VALLE, MAURIZIO;
1998

Abstract

In this paper a reconfigurable analog VLSI neural network architecture is presented. The analog architecture implements a Multi-Layer Perceptron whose topology can be programmed without any modification of the off-chip connections. The architecture is scaleable and modular since it is based on a single-chip configurable basic module. To obtain a robust behaviour with respect to noise and errors introduced in the computation by analog circuits, we use non-linear synapses and linear neurons as neural primitives.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11567/246702
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