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EnglishIn this paper a reconfigurable analog VLSI neural network architecture is presented. The analog architecture implements a Multi-Layer Perceptron whose topology can be programmed without any modification of the off-chip connections. The architecture is scaleable and modular since it is based on a single-chip configurable basic module. To obtain a robust behaviour with respect to noise and errors introduced in the computation by analog circuits, we use non-linear synapses and linear neurons as neural primitives.
A reconfigurable analog VLSI neural network architecture with non linear synapses / BO G.M.; CAVIGLIA D.D.; VALLE M.; STRATTA R.; TRUCCO E.. - In: INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS. - ISSN 0098-9886. - STAMPA. - 26(1998), pp. 307-315.
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| Titolo: | A reconfigurable analog VLSI neural network architecture with non linear synapses | |
| Autori: | ||
| Data di pubblicazione: | 1998 | |
| Rivista: | ||
| Citazione: | A reconfigurable analog VLSI neural network architecture with non linear synapses / BO G.M.; CAVIGLIA D.D.; VALLE M.; STRATTA R.; TRUCCO E.. - In: INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS. - ISSN 0098-9886. - STAMPA. - 26(1998), pp. 307-315. | |
| Abstract: | In this paper a reconfigurable analog VLSI neural network architecture is presented. The analog architecture implements a Multi-Layer Perceptron whose topology can be programmed without any modification of the off-chip connections. The architecture is scaleable and modular since it is based on a single-chip configurable basic module. To obtain a robust behaviour with respect to noise and errors introduced in the computation by analog circuits, we use non-linear synapses and linear neurons as neural primitives. | |
| Handle: | http://hdl.handle.net/11567/246702 | |
| Appare nelle tipologie: | 01.01 - Articolo su rivista |
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