CINECA IRIS Institutional Research Information System
IRIS è la soluzione IT che facilita la raccolta e la gestione dei dati relativi alle attività e ai prodotti della ricerca. Fornisce a ricercatori, amministratori e valutatori gli strumenti per monitorare i risultati della ricerca, aumentarne la visibilità e allocare in modo efficace le risorse disponibili.
EnglishIn this paper we present the analog architecture and the implementation of an on-chip learning Multi Layer Perceptron network. The learning algorithm is based on Back Propagation but it exhibits increased capabilities due to local learning rate management. A prototype chip (SLANP, Self-Learning Neural Processor) has been designed and fabricated in a CMOS 0.7 µm minimum channel length technology. We report the experimental results that confirm the functionality of the chip and the soundness of the approach. The SLANP performance compare favourably with those reported in the literature.
A Self-Learning Analog Neural Processor / BO G.M.; CAVIGLIA D.; VALLE M.. - In: IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS, COMMUNICATIONS AND COMPUTER SCIENCES. - ISSN 0916-8508. - STAMPA. - E85-A(2002), pp. 2149-2158.
Scheda prodotto non validato
Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo
| Titolo: | A Self-Learning Analog Neural Processor |
| Autori: | |
| Data di pubblicazione: | 2002 |
| Rivista: | |
| Citazione: | A Self-Learning Analog Neural Processor / BO G.M.; CAVIGLIA D.; VALLE M.. - In: IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS, COMMUNICATIONS AND COMPUTER SCIENCES. - ISSN 0916-8508. - STAMPA. - E85-A(2002), pp. 2149-2158. |
| Abstract: | In this paper we present the analog architecture and the implementation of an on-chip learning Multi Layer Perceptron network. The learning algorithm is based on Back Propagation but it exhibits increased capabilities due to local learning rate management. A prototype chip (SLANP, Self-Learning Neural Processor) has been designed and fabricated in a CMOS 0.7 µm minimum channel length technology. We report the experimental results that confirm the functionality of the chip and the soundness of the approach. The SLANP performance compare favourably with those reported in the literature. |
| Handle: | http://hdl.handle.net/11567/245544 |
| Appare nelle tipologie: | 01.01 - Articolo su rivista |
File in questo prodotto:
http://hdl.handle.net/11567/245544
Copyright © 2020