Neural recording systems are essential for understanding the brain and developing treatments for neurological disorders. Analog-to-digital converter (ADC) is among the required building blocks of neural recording systems, as they convert the brain's electrical signals into digital data that can be processed and analyzed by processing units. In this paper, a new nonlinear ADC for spike sorting in biomedical applications has been introduced. The ADC is implemented with MOSFET varactors and voltage-controlled oscillators (VCO). By exploiting the nonlinear capacitance characteristics of MOSFET varactors, the ADC has a parabolic quantization function to suppress background noise in biomedical signals. Furthermore, nonlinear digitization gives an effective resolution that is almost 0.11 bit more than its physical number of bits. The resolution of neural signals can vary from 3.1 bits in the low amplitude range to 9.11 bits in the high amplitude range. The circuit was designed and simulated using a 180 nm CMOS process, taking up 0.102 mm(2) of silicon area. While operating at the sampling frequency of 25 kS/s and a supply voltage of 1 Volt, this ADC dissipates 62.4 mu W.

A Nonlinear, Low-Power, VCO-Based ADC for Neural Recording Applications

Shokri, Reza;Aiello, Orazio;Caviglia, Daniele
2023-01-01

Abstract

Neural recording systems are essential for understanding the brain and developing treatments for neurological disorders. Analog-to-digital converter (ADC) is among the required building blocks of neural recording systems, as they convert the brain's electrical signals into digital data that can be processed and analyzed by processing units. In this paper, a new nonlinear ADC for spike sorting in biomedical applications has been introduced. The ADC is implemented with MOSFET varactors and voltage-controlled oscillators (VCO). By exploiting the nonlinear capacitance characteristics of MOSFET varactors, the ADC has a parabolic quantization function to suppress background noise in biomedical signals. Furthermore, nonlinear digitization gives an effective resolution that is almost 0.11 bit more than its physical number of bits. The resolution of neural signals can vary from 3.1 bits in the low amplitude range to 9.11 bits in the high amplitude range. The circuit was designed and simulated using a 180 nm CMOS process, taking up 0.102 mm(2) of silicon area. While operating at the sampling frequency of 25 kS/s and a supply voltage of 1 Volt, this ADC dissipates 62.4 mu W.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11567/1206936
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