Fully Synthesizable Low-Area Digital-to-Analog Converter with Graceful Degradation and Dynamic Power-Resolution Scaling

In this paper, a fully synthesizable digital-to-analog converter (DAC) is proposed. Based on a digital standard cell approach, the proposed DAC allows very low design effort and enables digital-like shrinkage across CMOS generations, low area at down-scaled technologies, and operation down to near-threshold voltages. The proposed DAC can operate at supply voltages that are significantly lower and/or at clock frequencies that are significantly greater than the intended design point, at the expense of moderate resolution degradation. In a 12-bit 40nm testchip, graceful degradation of 0.3 bit/100 mV is achieved when VDD is over-scaled down to 0.8 V, and 1.4 bit/100 mV when further scaled down to 0.6 V. The proposed DAC enables dynamic power-resolution tradeoff with three times (two times) power saving for 1-bit resolution degradation at iso-sample rate (iso-resolution). A 12-bit DAC testchip designed with a fully automated standard cell flow in 40 nm consumes 55 μW at 27 kS/s (9.1 μW at 13.5 kS/s) at a compact area of 500 μm2 and low voltage of 0.55 V.