VALLE, MAURIZIO

VALLE, MAURIZIO  

100026 - Dipartimento di Ingegneria navale, elettrica, elettronica e delle telecomunicazioni  

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Titolo Data di pubblicazione Autore(i) File
1-D Convolutional Neural Networks for Touch Modalities Classification 1-gen-2021 Gianoglio, C.; Ragusa, E.; Zunino, R.; Valle, M.
153dB dynamic range calibration-less gas sensor interface circuit with quasi-digital output 1-gen-2017 Hijazi, Zeinab; Grassi, Marco; Caviglia, Daniele D.; Valle, Maurizio
A behavioral model for the non-linear on-resistance in sample-and-hold analog switches 1-gen-2005 Prodanov, William; Valle, Maurizio
A Current Mode CMOS Multi Layer Perceptron Chip 1-gen-1996 G. M., Bo; Caviglia, Daniele; Valle, Maurizio
A fully-automatic CAD toolbox for a MOS drain current model and its parameters extraction 1-gen-2006 Prodanov, William; Valle, Maurizio
A generic framework for failure modes and effects analysis of automotive networks 1-gen-2011 Muller, Candice; Valle, Maurizio; E., Armengaud; A., Tengg
A hardware implementation of hierarchical neural networks for real-time quality control systems in industrial applications 1-gen-1997 Baratta, D.; Bo, G. M.; Caviglia, Daniele; Valle, Maurizio; Canepa, G.; Parenti, R.; Pernio, C.
A mixed mode perceptron cell for VLSI Neural Networks 1-gen-2001 Camboni, F.; Valle, Maurizio
A Mixed-Mode behavioral model for a Controller-Area-Network bus transceiver: a case study 1-gen-2007 W., Prodanov; Valle, Maurizio; R., Buzas; H., Pierscinski
A mixed-precision binary neural network architecture for touch modality classification 1-gen-2021 Younes, H.; Ibrahim, A.; Rizk, M.; Valle, M.
A Novel Current-Mode Very Low Power Analog CMOS Four Quadrant Multiplier 1-gen-2005 M., Gravati; Valle, Maurizio; G., Ferri; N., Guerrini; L., Reyes
A Novel Tactile Sensing System for Robotic Tactile Perception of Object Properties 1-gen-2023 Amin, Y.; Gianoglio, C.; Valle, M.
A Pipelined Implementation of the n-mode Tensor-Matrix Multiplication 1-gen-2022 Ragusa, Edoardo; Gianoglio, Christian; Zunino, Rodolfo; Valle, Maurizio; Gastaldo, Paolo
A scheme for measuring and extracting level-1 parameter of FET device applied toward POSFET sensors array 1-gen-2011 Sinha, ARUN KUMAR; Valle, Maurizio
A VLSI architecture for a Prolog machine 1-gen-1988 Valle, Maurizio; DE GLORIA, Alessandro; Chirico, M.; Antognetti, P.
A VLSI architecture for weight perturbation on chip learning implementation 1-gen-2000 Francesco, Diotalevi; Valle, Maurizio; Gianmarco, Bo; Caviglia, Daniele
A Web-Based Courseware On Microelectronics 1-gen-1998 Caviglia, Daniele; G., Da Bormida; Ponta, Domenico; M., Terrizzano; Valle, Maurizio
Alessandro De Gloria, a Pioneer in Electronic Engineering Applications 1-gen-2024 Bellotti, F.; Bricco, E.; Bruzzone, A.; Caviglia, D.; Di Zitti, E.; Gastaldo, P.; Grosso, D.; Magnani, L.; Olivieri, M.; Raggio, M.; Valle, M.; Verri, A.; Berta, R.
Algorithmic level approximate computing for machine learning classifiers 1-gen-2019 Younes, H.; Ibrahim, A.; Rizk, M.; Valle, M.
AN ANALOG ON-CHIP LEARNING CIRCUIT ARCHITECTURE OF THE WEIGHTPERTURBATION ALGORITHM 1-gen-2000 F., Diotalevi; Valle, Maurizio; G. M., Bo; E., Biglieri; Caviglia, Daniele