A reconfigurable mixed-mode perceptron building block for VLSI Neural Networks is presented. The proposed architecture is suitable for high-speed low-power Neural Networks like Multi Layer Perceptrons. The proposed system uses a mixed-signal multiplier technique for directly multiplying the digital weights and the analog input signals. A 5-input 6-bits design has been simulated in a 0.6μm CMOS process. The perceptron operates up to 125 MHz and dissipates 2 mW. The power efficiency is 300 MCPS/mW.
A mixed mode perceptron cell for VLSI Neural Networks
VALLE, MAURIZIO
2001-01-01
Abstract
A reconfigurable mixed-mode perceptron building block for VLSI Neural Networks is presented. The proposed architecture is suitable for high-speed low-power Neural Networks like Multi Layer Perceptrons. The proposed system uses a mixed-signal multiplier technique for directly multiplying the digital weights and the analog input signals. A 5-input 6-bits design has been simulated in a 0.6μm CMOS process. The perceptron operates up to 125 MHz and dissipates 2 mW. The power efficiency is 300 MCPS/mW.
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