Digital architectures for the circuit realization of multivariate piecewise-linear (PWL) functions are reviewed and compared. The output of the circuits is a digital word representing the value of the PWL function at the n-dimensional input. In particular, we propose two architectures with different levels of parallelism/complexity. PWL functions with n=3 inputs are implemented on an FPGA and experimental results are shown. The accuracy in the representation of PWL functions is tested through three benchmark examples, two concerning three-variate static functions and one concerning a dynamical control system defined by a bi-variate PWL function.
Digital architectures for the circuit implementation of PWL multi-variate functions: two FPGA implementations
STORACE, MARCO;
2011-01-01
Abstract
Digital architectures for the circuit realization of multivariate piecewise-linear (PWL) functions are reviewed and compared. The output of the circuits is a digital word representing the value of the PWL function at the n-dimensional input. In particular, we propose two architectures with different levels of parallelism/complexity. PWL functions with n=3 inputs are implemented on an FPGA and experimental results are shown. The accuracy in the representation of PWL functions is tested through three benchmark examples, two concerning three-variate static functions and one concerning a dynamical control system defined by a bi-variate PWL function.
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