The analog VLSI implementation of an on-chip learning neural network is discussed in this paper. The multi layer perceptron paradigm and back propagation learning rule have been mapped onto analog circuits. A local learning rate adaptation rule has been also considered to improve the training performance (i.e., fast convergence speed). Experimental results confirm the chip functionality and the soundness of our approach
An Experimental Analog CMOS Self-Learning Chip
CAVIGLIA, DANIELE;VALLE, MAURIZIO
1999-01-01
Abstract
The analog VLSI implementation of an on-chip learning neural network is discussed in this paper. The multi layer perceptron paradigm and back propagation learning rule have been mapped onto analog circuits. A local learning rate adaptation rule has been also considered to improve the training performance (i.e., fast convergence speed). Experimental results confirm the chip functionality and the soundness of our approach
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