In this paper we present the analog CMOS design of a multi-layer-perceptron network with on-chip by-pattern back-propagation learning. The learning algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient in terms of convergence speed. Circuit simulation results validate the network behavior
Design of an Analog CMOS Self-Learning Multilayer Perceptron Chip
CAVIGLIA, DANIELE;VALLE, MAURIZIO
1998-01-01
Abstract
In this paper we present the analog CMOS design of a multi-layer-perceptron network with on-chip by-pattern back-propagation learning. The learning algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient in terms of convergence speed. Circuit simulation results validate the network behavior
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