Highly Linear, Digital OTA With Modified Input Stage

This paper presents a digital OTA topology with a modified input stage, leveraging a complementary Muller stage and Muller- based current mirrors to increase the linearity. By employing a 180-nm standard CMOS technology and operating with a supply voltage down to 0.3 V, simulations demonstrate a 54.5-dB gain and a 265 Hz gain bandwidth product when driving a 150-pF capacitive load. In comparison to other ultra-low-voltage OTAs reported so far in the literature, the proposed work leads to an enhancement in signal linearity (total harmonic distortion is 0.7% at 0.3V and 0.3% at 0.5V) and in the common mode and power-supply rejection ratios, to respectively 93dB and 63.9dB.