In this paper we present the analog CMOS design of a Multi-Layer-Perceptron network with on-chip by-pattern Back-Propagation learning. The learning algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient in terms of convergence speed. Circuit simulation results validate the network behavior.
Design of an analog CMOS self-learning MLP chip
CAVIGLIA, DANIELE;VALLE, MAURIZIO
1998-01-01
Abstract
In this paper we present the analog CMOS design of a Multi-Layer-Perceptron network with on-chip by-pattern Back-Propagation learning. The learning algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient in terms of convergence speed. Circuit simulation results validate the network behavior.
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