Soft-Max (SM) operation in vector signal processing usually serves to remap an input distribution within a predetermined range; by a scalar (gain) parameter one can adjust the sharpness of the overall process. Thus, to exhibit practical interest, design approaches to SM circuitry should be consistent and, at the same time, allow dynamic gain control. Therefore, a preliminary analysis applies a power-series expansion to Soft-Max processing and derives both an analytical upper bound to the resulting approximation error, and a convenient mathematical approach to gain control. Theoretical achievements drive the subsequent current-mode circuit design, which yields a modular architecture that enhances overall parallelism. For simplicity, a digital mechanism supports the dynamic gain control in Soft-Max processing, but analogue solutions are also feasible. Simulation results in both static and dynamic tests confirmed the accuracy and effectiveness of the proposed design method. The cell-based circuit architecture sharply reduces VLSI complexity and limits power consumption.

Soft-Max circuit design with adjustable gain

ZUNINO, RODOLFO
2006-01-01

Abstract

Soft-Max (SM) operation in vector signal processing usually serves to remap an input distribution within a predetermined range; by a scalar (gain) parameter one can adjust the sharpness of the overall process. Thus, to exhibit practical interest, design approaches to SM circuitry should be consistent and, at the same time, allow dynamic gain control. Therefore, a preliminary analysis applies a power-series expansion to Soft-Max processing and derives both an analytical upper bound to the resulting approximation error, and a convenient mathematical approach to gain control. Theoretical achievements drive the subsequent current-mode circuit design, which yields a modular architecture that enhances overall parallelism. For simplicity, a digital mechanism supports the dynamic gain control in Soft-Max processing, but analogue solutions are also feasible. Simulation results in both static and dynamic tests confirmed the accuracy and effectiveness of the proposed design method. The cell-based circuit architecture sharply reduces VLSI complexity and limits power consumption.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11567/222116
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