This paper deals with analog VLSI architectures addressed to the implementation of smart adaptive systems on silicon. In particular, we addressed the implementation of artificial neural networks with on-chip learning algorithms with the goal of efficiency in terms of scalability, modularity, computational density, real time operation and power consumption. We present the analog circuit architecture of a feed-forward network with on-chip weight perturbation learning in CMOS technology. Novelty of the approach lies in the circuit implementation of the feed-forward neural primitives and on the overall analog circuit architecture. The proposed circuits feature very low power consumption and robustness with respect to noise effects. We extensively tested the analog architecture with simulations at transistor level by using the netlist extracted from the physical design. The results compare favourably with those reported in the open literature. In particular, the architecture exhibits very high power efficiency and computational density and remarkable modularity and scalability features. The proposed approach is aimed to the implementation of embedded intelligent systems for ubiquitous computing.

A Dedicated Very Low Power Analog VLSI Architecture for Smart Adaptive Systems

DIOTALEVI, FRANCESCO;VALLE, MAURIZIO
2004

Abstract

This paper deals with analog VLSI architectures addressed to the implementation of smart adaptive systems on silicon. In particular, we addressed the implementation of artificial neural networks with on-chip learning algorithms with the goal of efficiency in terms of scalability, modularity, computational density, real time operation and power consumption. We present the analog circuit architecture of a feed-forward network with on-chip weight perturbation learning in CMOS technology. Novelty of the approach lies in the circuit implementation of the feed-forward neural primitives and on the overall analog circuit architecture. The proposed circuits feature very low power consumption and robustness with respect to noise effects. We extensively tested the analog architecture with simulations at transistor level by using the netlist extracted from the physical design. The results compare favourably with those reported in the open literature. In particular, the architecture exhibits very high power efficiency and computational density and remarkable modularity and scalability features. The proposed approach is aimed to the implementation of embedded intelligent systems for ubiquitous computing.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11567/208206
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