We present and discuss the major results of our research activity aimed to the analog VLSI implementation of on-chip learning neural networks. In particular we present the SLANP (self learning neural processor) chip results. The SLANP architecture implements an on-chip learning multilayer perceptron network. The learning algorithm is based on the back propagation but it exhibits increased capabilities due to the local learning rate management. A prototype chip has been designed and fabricated in a CMOS 0.7 μm minimum channel length technology. The experimental results confirm the functionality of the chip and the soundness of the approach. The SLANP performance compares favorably with that reported in the literature

An on-chip learning neural network

CAVIGLIA, DANIELE;VALLE, MAURIZIO
2000

Abstract

We present and discuss the major results of our research activity aimed to the analog VLSI implementation of on-chip learning neural networks. In particular we present the SLANP (self learning neural processor) chip results. The SLANP architecture implements an on-chip learning multilayer perceptron network. The learning algorithm is based on the back propagation but it exhibits increased capabilities due to the local learning rate management. A prototype chip has been designed and fabricated in a CMOS 0.7 μm minimum channel length technology. The experimental results confirm the functionality of the chip and the soundness of the approach. The SLANP performance compares favorably with that reported in the literature
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11567/204499
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