This chapter describes an analog VLSI implementation of a multilayer perceptron neural network with on-chip back propagation learning. Local adaptation of the learning rate offers fast convergence. Experimental results from a chip fabricated in the ATMEL ES2 ECPD07 0.7 um CMOS process demonstrate learning of a 2-input exclusive-or task in 32 ms.
Analog VLSI On-Chip Learning Neural Network with Learning Rate Adaptation
CAVIGLIA, DANIELE;VALLE, MAURIZIO
1999-01-01
Abstract
This chapter describes an analog VLSI implementation of a multilayer perceptron neural network with on-chip back propagation learning. Local adaptation of the learning rate offers fast convergence. Experimental results from a chip fabricated in the ATMEL ES2 ECPD07 0.7 um CMOS process demonstrate learning of a 2-input exclusive-or task in 32 ms.
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