Approximate computing circuits are considered as a promising solution to reduce the power consumption in embedded data processing. This paper proposes an FPGA implementation for an approximate multiplier based on inexact adder circuits. The performance of the proposed multiplier is evaluated by comparing the power consumption, the accuracy of computation, and the time delay with those of an approximate multiplier based on exact adder presented in literature. Results reports a power saving up to 17.39% with an improvement in time delay by 13.49%, at cost of less than 5% of accuracy loss. © 2017 IEEE.
|Titolo:||Approximate multipliers based on inexact adders for energy efficient data processing|
|Data di pubblicazione:||2017|
|Appare nelle tipologie:||04.01 - Contributo in atti di convegno|