Analog VLSI Hardware implementation of a supervised learning algorithm

In this chapter, we introduce an analog chip hosting a self-learning neural network with local learning rate adaptation. The neural architecture has been validated through intensive simulation on the recognition of handwritten characters. It has hence been mapped onto an analog architecture. The prototype chip implementing the whole on-chip learning neural architecture has been designed and fabricated by using a 0.7 um channel length CMOS technology, Experimental results on two learning tasks confirm the functionality of the chip and the soundness of the approach. The chip features a peak performance of 2.65  10^6 connections updated per second.