A hierarchical graph-based model, called a structured hypergraph with ports (SPH-graph), is presented, that provides a structural description of VLSI objects at different levels of abstraction. The relationship between hardware description languages and the SPH-graph model are investigated by considering the VHSIC hardware description language (VHDL). It is shown, through an example, how a structural VHDL description of a hardware entity can be mapped on the model by using a basic set of primitives for SPH-graph manipulation.
SPH-Graph: A model to support VLSI design
Ancona M.;Clematis A.;De Floriani L.;Puppo E.
1988-01-01
Abstract
A hierarchical graph-based model, called a structured hypergraph with ports (SPH-graph), is presented, that provides a structural description of VLSI objects at different levels of abstraction. The relationship between hardware description languages and the SPH-graph model are investigated by considering the VHSIC hardware description language (VHDL). It is shown, through an example, how a structural VHDL description of a hardware entity can be mapped on the model by using a basic set of primitives for SPH-graph manipulation.
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