Modelling mismatch effects in CMOS translinear loops and current mode multipliers

MOS translinear circuits can be effectively employed in systems and applications demanding very low power consumption and low operating frequency ranges (i.e. few kHzs) e.g. in bioelectronics and neuroengineering. Nevertheless weak inversion mismatch modelling for design applications is still lacking. In this paper we present a mismatch model for MOS translinear loops and current mode multipliers which accounts for non linearity and accuracy. The model has been experimentally validated and the results are reported. We report also an example of the application of the model to the statistical accuracy analysis of the MOS current mode Gilbert multiplier in the circuit design phase.