In this paper we introduce a digital architecture implementing piecewise-affine functions defined over domains partitioned into polytopes: the functions are linear affine over each polytope. The polytope containing the input vector is found by exploring a previously constructed binary search tree. Once the polytope is detected, the function is evaluated by addressing an affine map whose coefficients are stored in a memory. The architecture has been implemented on FPGA and experimental results for a benchmark example are shown.
Circuit Implementation of Piecewise-Affine Functions Based on a Binary Search Tree
OLIVERI, ALBERTO;POGGI, TOMASO;STORACE, MARCO
2009-01-01
Abstract
In this paper we introduce a digital architecture implementing piecewise-affine functions defined over domains partitioned into polytopes: the functions are linear affine over each polytope. The polytope containing the input vector is found by exploring a previously constructed binary search tree. Once the polytope is detected, the function is evaluated by addressing an affine map whose coefficients are stored in a memory. The architecture has been implemented on FPGA and experimental results for a benchmark example are shown.
File in questo prodotto:
Non ci sono file associati a questo prodotto.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
