A central issue in computational intelligence is the training phase of a learning machine. In classification problems, in particular, Support Vector Machines are one of the most effective tools. In this work an analog low-complexity circuital implementation is proposed to address the learning stage of SVMs. The circuit is a co-content minimization network based on a suitable SVM formulation embedding bias removal. Moreover the circuit complexity (i.e. the density of the kernel matrix) is effectively controlled by resorting to a proper kernel function. Experimental evidence shows the effectiveness of the proposed approach
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Titolo: | Circuit Implementation of SVM Training |
Autori: | |
Data di pubblicazione: | 2009 |
Handle: | http://hdl.handle.net/11567/238488 |
ISBN: | 9781424435531 |
Appare nelle tipologie: | 04.01 - Contributo in atti di convegno |