An abstract hypercube architecture made up of computing elements (nodes) has been simulated, in which each node is able to manage both the computation of data and the communications with the other nodes of the architecture. This is achieved by providing each node with a proper set of instructions, which are broadcast (according to the SIMD paradigm) from a master processor to all nodes. The instructions are arithmetic, communication, and system instructions; the user can control the instruction execution through the system instructions. Nodes are clocked according to a main cycle, which includes: 1) injection of the messages to be exchanged between two nodes into a data buffer, 2) two cycles for each hypercube dimension, during which the messages present in the data buffer are transmitted along the hypercube, 3) a delivery cycle, during which the received messages are delivered to the related memory locations. This architecture has been evaluated via a set of computer simulations performed to test the communication capabilities of the machine. Several parameters have been taken into account in order to obtain graphics describing the way in which the communication load affects such entities as throughput, depletion time, number of sent messages, mean delay, and number of router overflows. The parameters considered refer to the number of messages managed by the router, the program implemented, the use of alternative paths for messages, and the way (random or fixed) in which communications along the hypercube dimensions are scheduled.

Evaluation of Communication Performances in Hypercube Architectures

CURATELLI, FRANCESCO
1992-01-01

Abstract

An abstract hypercube architecture made up of computing elements (nodes) has been simulated, in which each node is able to manage both the computation of data and the communications with the other nodes of the architecture. This is achieved by providing each node with a proper set of instructions, which are broadcast (according to the SIMD paradigm) from a master processor to all nodes. The instructions are arithmetic, communication, and system instructions; the user can control the instruction execution through the system instructions. Nodes are clocked according to a main cycle, which includes: 1) injection of the messages to be exchanged between two nodes into a data buffer, 2) two cycles for each hypercube dimension, during which the messages present in the data buffer are transmitted along the hypercube, 3) a delivery cycle, during which the received messages are delivered to the related memory locations. This architecture has been evaluated via a set of computer simulations performed to test the communication capabilities of the machine. Several parameters have been taken into account in order to obtain graphics describing the way in which the communication load affects such entities as throughput, depletion time, number of sent messages, mean delay, and number of router overflows. The parameters considered refer to the number of messages managed by the router, the program implemented, the use of alternative paths for messages, and the way (random or fixed) in which communications along the hypercube dimensions are scheduled.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11567/184576
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