Sfoglia per Autore
A VLSI architecture for a Prolog machine
1988-01-01 Valle, Maurizio; DE GLORIA, Alessandro; Chirico, M.; Antognetti, P.
Simulation of Neural Networks for the Resolution of Optimization Problems
1989-01-01 Bisio, G. M.; Caviglia, Daniele; Chirico, M; Curatelli, Francesco; Valle, Maurizio
Analysis of neural algorithms for parallel architectures
1989-01-01 DI ZITTI, Ermanno; Bisio, Giacomo; Caviglia, Daniele; Chirico, Marco; Parodi, Giancarlo
A Distributed DRC program for IC Layout Verification
1990-01-01 Paganini, M; Chirico, M; Caviglia, Daniele; Curatelli, Francesco; Barzaghi, M; Bisio, G. M.
An evaluation system for Prolog dedicated processors
1990-01-01 DE GLORIA, Alessandro; Valle, Maurizio; Chirico, M.; Moneta, C.
Transputer Application for Integrated Circuit Layout Verification
1991-01-01 Chirico, M.; Caviglia, Daniele; Barzaghi, M.; Curatelli, Francesco
Parallel Symbolic Compaction of Digital CMOS Cells on a 2-D Mesh of Transputers
1991-01-01 Caviglia, Daniele; Barzaghi, M; Chirico, M; Curatelli, Francesco; Bisio, G. M.; Prossen, S; Stefani, L.
Implementation of an efficient algorithm for VLSI design rule checking on a 2-D mesh of transputers
1991-01-01 Caviglia, Daniele; Paganini, M.; Chirico, M.; Curatelli, Francesco; Barzaghi, M.; Bisio, Giacomo
Implementation of Efficient Strategies for Cell Generation in VLSI Design
1992-01-01 Curatelli, Francesco; Caviglia, Daniele; Bisio, G. M.; Chirico, M.
Optimization Strategies for the Symbolic Compaction of Digital CMOS Cells
1992-01-01 Curatelli, Francesco; Caviglia, Daniele; Chirico, M; Bisio, G. M.
A Parallel Approach to Symbolic Layout Compaction of Digital CMOS Cells
1992-01-01 Barzaghi, M.; Caviglia, Daniele; Chirico, M.; Curatelli, Francesco; Bisio, G. M.; Prossen, S.; Stefani, L.
Optimization Strategies in Symbolic Compaction
1993-01-01 Curatelli, Francesco; Caviglia, Daniele; Chirico, M.; Bisio, G. M.
CAD Support for System-level Synthesis
1993-01-01 Cornero, M; Chirico, M; Curatelli, Francesco; M. BISIO, G.
System-Level Modeling of an ATM Node in VHDL
1994-01-01 Cornero, M; Marchese, Mario; Chirico, M; Curatelli, Francesco
A Linear Rotation Based Solution of Large Systems on a Transputer Array
1995-01-01 Chirico, Marco; DI ZITTI, Ermanno; Bisio, Giacomo
Efficient Technique for Partitioning and Programming Linear Algebra Algorithms on Concurrent VLSI Architectures
1995-01-01 DI ZITTI, Ermanno; Chirico, M.; Curatelli, Francesco; Bisio, G. M.
Specification and Management of Timing Constraints in Behavioral VHDL
1996-01-01 Curatelli, Francesco; Mangeruca, L; Chirico, M.
Real-time Multi-tasking in Software Synthesis for DSP Based Systems
1996-01-01 Thoen, F; VAN DER STEEN, J; Goossens, G; Curatelli, Francesco; Mangeruca, L; Chirico, M.
Implementation Issues for Congestion Control in ATM Networks
1996-01-01 Marchese, Mario; Curatelli, Francesco; Chirico, M; Mangeruca, L.
RAIN: Redundant Array of Inexpensive workstations for Neurocomputing
1997-01-01 Anguita, Davide; Chirico, M.; Scapolla, A. M.; Parodi, G.
Titolo | Data di pubblicazione | Autore(i) | File |
---|---|---|---|
A VLSI architecture for a Prolog machine | 1-gen-1988 | Valle, Maurizio; DE GLORIA, Alessandro; Chirico, M.; Antognetti, P. | |
Simulation of Neural Networks for the Resolution of Optimization Problems | 1-gen-1989 | Bisio, G. M.; Caviglia, Daniele; Chirico, M; Curatelli, Francesco; Valle, Maurizio | |
Analysis of neural algorithms for parallel architectures | 1-gen-1989 | DI ZITTI, Ermanno; Bisio, Giacomo; Caviglia, Daniele; Chirico, Marco; Parodi, Giancarlo | |
A Distributed DRC program for IC Layout Verification | 1-gen-1990 | Paganini, M; Chirico, M; Caviglia, Daniele; Curatelli, Francesco; Barzaghi, M; Bisio, G. M. | |
An evaluation system for Prolog dedicated processors | 1-gen-1990 | DE GLORIA, Alessandro; Valle, Maurizio; Chirico, M.; Moneta, C. | |
Transputer Application for Integrated Circuit Layout Verification | 1-gen-1991 | Chirico, M.; Caviglia, Daniele; Barzaghi, M.; Curatelli, Francesco | |
Parallel Symbolic Compaction of Digital CMOS Cells on a 2-D Mesh of Transputers | 1-gen-1991 | Caviglia, Daniele; Barzaghi, M; Chirico, M; Curatelli, Francesco; Bisio, G. M.; Prossen, S; Stefani, L. | |
Implementation of an efficient algorithm for VLSI design rule checking on a 2-D mesh of transputers | 1-gen-1991 | Caviglia, Daniele; Paganini, M.; Chirico, M.; Curatelli, Francesco; Barzaghi, M.; Bisio, Giacomo | |
Implementation of Efficient Strategies for Cell Generation in VLSI Design | 1-gen-1992 | Curatelli, Francesco; Caviglia, Daniele; Bisio, G. M.; Chirico, M. | |
Optimization Strategies for the Symbolic Compaction of Digital CMOS Cells | 1-gen-1992 | Curatelli, Francesco; Caviglia, Daniele; Chirico, M; Bisio, G. M. | |
A Parallel Approach to Symbolic Layout Compaction of Digital CMOS Cells | 1-gen-1992 | Barzaghi, M.; Caviglia, Daniele; Chirico, M.; Curatelli, Francesco; Bisio, G. M.; Prossen, S.; Stefani, L. | |
Optimization Strategies in Symbolic Compaction | 1-gen-1993 | Curatelli, Francesco; Caviglia, Daniele; Chirico, M.; Bisio, G. M. | |
CAD Support for System-level Synthesis | 1-gen-1993 | Cornero, M; Chirico, M; Curatelli, Francesco; M. BISIO, G. | |
System-Level Modeling of an ATM Node in VHDL | 1-gen-1994 | Cornero, M; Marchese, Mario; Chirico, M; Curatelli, Francesco | |
A Linear Rotation Based Solution of Large Systems on a Transputer Array | 1-gen-1995 | Chirico, Marco; DI ZITTI, Ermanno; Bisio, Giacomo | |
Efficient Technique for Partitioning and Programming Linear Algebra Algorithms on Concurrent VLSI Architectures | 1-gen-1995 | DI ZITTI, Ermanno; Chirico, M.; Curatelli, Francesco; Bisio, G. M. | |
Specification and Management of Timing Constraints in Behavioral VHDL | 1-gen-1996 | Curatelli, Francesco; Mangeruca, L; Chirico, M. | |
Real-time Multi-tasking in Software Synthesis for DSP Based Systems | 1-gen-1996 | Thoen, F; VAN DER STEEN, J; Goossens, G; Curatelli, Francesco; Mangeruca, L; Chirico, M. | |
Implementation Issues for Congestion Control in ATM Networks | 1-gen-1996 | Marchese, Mario; Curatelli, Francesco; Chirico, M; Mangeruca, L. | |
RAIN: Redundant Array of Inexpensive workstations for Neurocomputing | 1-gen-1997 | Anguita, Davide; Chirico, M.; Scapolla, A. M.; Parodi, G. |
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